The present invention relates to circuit technology for preventing electrostatic damage of semiconductor devices.
Semiconductor devices (semiconductor integrated circuits) are known that have a first input protection circuit for guiding positive electrostatic discharges, that are applied from the outside, to a signal input terminal to a power source line, and a second input protection circuit for guiding negative electrostatic discharges, that are applied from the outside to that signal input terminal, to a ground line. The first and the second input protection circuit are respectively made of diodes, MOS transistors or bipolar transistors (see JP H09-139466A).
It is possible to configure a delay circuit with a plurality of cascaded inverters. The inverters may be configured by P-channel MOS transistors and N-channel MOS transistors. If the above-noted first and second input protection circuits are used for a semiconductor device having such a delay circuit, then the first-stage inverter, which is directly connected to the signal input terminal, can be protected from gate insulation damage when electrostatic discharges are applied to the signal input terminal. However, when positive electrostatic discharges are applied to the signal input terminal while the power source terminal and the ground terminal are open (no-voltage state), for example in the assembly line for the appliance in which the semiconductor device is to be mounted, then the internal inverters may suffer gate insulation damage.